1. Field of the Invention
The present invention relates to structures and methods of fabricating a dynamic random access memory having a high capacitance stacked capacitor.
2. Description of the Prior Art
Semiconductor device manufactures are continually pressured to increase effective device densities in order to remain cost competitive. As a result, Very Large Scale Integration (VLSI) and Ultra Large Scale Integration (ULSI) technologies have entered the sub-micron realm of structural dimension and now are approaching physical limits in the nanometer feature size range. In the near future, absolute atomic physical limits will be reached in the conventional two-dimensional approach to semiconductor device design. Traditionally, dynamic random access memory (DRAM) designers have faced the severest of challenges in advancing technologies. For example, designers of 64K DRAMs were perplexed to learn that a practical physical limit to charge capacity of storage capacitors had already been reached due to the minimum charge necessary to sense signals in the presence of environmental or particulate radiation inherently present in fabrication materials. Storage capacitors in the range of 50 femtofarads are now considered to be a physical limit. From a practical view, this limitation prevented the scaling of DRAM capacitors. Reduction of the surface area of a semiconductor substrate utilized by the storage capacitor has also been severely restricted. Large DRAM devices are normally silicon based, and each cell typically embodies a single MOS field effect transistor with its source connected to a storage capacitor. This large integration of DRAMs has been accomplished by a reduction in individual cell size. However, a decrease in storage capacitance, which results from the reduction in cell size, leads to draw backs, such as a lowering source/drain ratio and undesirable signal problems in terms of reliability.
Due to decreases in the thickness of capacitor materials, existing 1 Megabit (1 MBit) DRAM technologies utilize a planar device in circuit design. Beginning with 4 MBit DRAMs, the world of three-dimensional design has been explored to the extent that the simple single device/capacitor memory cell has been altered to provide the capacitor in a vertical dimension. In such designs the capacitor has been formed in a trench in the surface of the semiconductor substrate. In yet denser designs, other forms of capacitor design are proposed, such as stacking the capacitor above the transfer device.
There are two main approaches in producing capacitors for DRAM's, some manufacturers pursuing trench capacitors built into the crystalline silicon wafer, and other manufacturers pursuing stacked capacitors in which the capacitor is fabricated on top of the wafer surface. In the case of the trench capacitor, its extendibility is in doubt since it is extremely difficult to etch about 0.15-0.25 micrometer wide trenches well over 10 micrometers deep, as well as to then fabricate ultra thin dielectric layers on the trench surface, fill the trench, etc. On the other hand, the use of a stacked capacitor permits a variety of new process options, for example, in the choice of electrode material (polysilicon, silicide, etc.).
A stacked capacitor is fabricated by forming the stacked capacitor structures laying over the gate electrode on active, field oxide, and diffusion regions. The processing of such structures has become very complicated and require lithography and etching steps that are not in step with the very small dimensions required in the present and future state of the art. Although there has been much work done in accomplishing these small size devices and increased capacitance therein, there is still great need for devices with even greater capacitance for a given space in order to achieve even greater packing densities and improve the DRAM products of the future.
Efforts to maintain or increase the storage capacitance in memory cells with greater packing densities is evident in Oehrleim et al. U.S. Pat. No. 5,155,657 which discloses a capacitor comprising one or more main vertical trenches and one or more lateral trenches extending off a main vertical trench. The lateral trenches effectively increase the capacitance of the capacitor.
Tseng U.S. Pat. No. 5,126,916 discloses a stacked capacitor DRAM cell which produces a stacked capacitor over the gates and source areas of a device. Also, Tseng U.S. Pat. No. 5,192,702 discloses a self-aligned cylindrical stacked capacitor DRAM cell.
However, a need continues to exist in the art for an easy to manufacture stacked capacitor having a larger surface area so that the capacitor's capacitance is increased in high density DRAM, without increasing the area occupied by the capacitor structure on or in a silicon substrate.